Field of the Invention
The invention pertains to a dynamic memory with single-cycle writing of a field of logic states. It finds application in the setting up of large-capacity memory units which may be isolated or integrated into a central processing unit.
In the prior art, a dynamic memory, to be charged, first has to be addressed, and then a logic state is transmitted to the desired address. Thus, for an address cycle, only one address is accessible at a time. By increasing the number of the addressable rows, it is possible to increase the quantity of logic states entered in one cycle for a dynamic memory capacity, but the writing of a complete field is a long process. In particular, this arrangement is disadvantageous for the initialization of image memories used by graphic processors.
One of the aims of the present invention is to propose a special arrangement by which a field of bits of a given value can be written in a single writing cycle.
Furthermore, the invention cannot be identified with the approach that consists in increasing the number of the addressing means of the dynamic memory to increase the overall writing speed. On the contrary, as compared with this type of solution, the invention proposes a simplier and less expensive arrangement which does not take up much of the useful surface of silicon on the integrated circuit in which the dynamic memory of the invention is implanted.